Semiconductor & VLSI

Chemical Mechanical Planarization (CMP) Dummy Metal Fill Calculator

Model Prestonian material removal ($MRR$), pattern density gradients ($\rho$), dielectric erosion, copper wire dishing depth ($h_{dish}$), and staggered vector dummy fill tiles for semiconductor chip prepress.

1. Input Parameters

Dummy Fill Tile Size $W_{fill} \times H_{fill}$ (µm):

Square or rectangular floating metal fill polygon width.

Tile-to-Tile Spacing / Pitch Gap $S_{tile}$ (µm):

Spacing between adjacent dummy metal tiles.

Active Circuit Pattern Density $\rho_{active}$ (%):

Raw active interconnect metal coverage before dummy fill insertion.

Target Design Rule CMP Density Window (%):

CMP Head Downforce Pressure $P$ (psi):

Polishing pad downward pressure applied to the wafer.

Platen Relative Velocity $V$ (m/s):

Linear sliding velocity between CMP pad and wafer surface.

2. Calculation Results

Dummy Fill Area Density

0.0%

Total Post-Fill Density

0.0%

Estimated Copper Dishing

0.0 nm

DRC CMP Density Compliance

DRC Compliant (Pass)

Prestonian MRR

0.0 nm/min

Dielectric Erosion Depth

0.0 nm

3. Dynamic Visualizer & CAM Preview

4. Engineering Notes & Physics Specifications

Preston's Polishing Law & Pattern Density Dishing Models:

Preston's Law of Polishing: Material removal rate across the wafer is proportional to downforce pressure and relative velocity: $MRR = K_p \cdot P \cdot V$.
Density Gradient & Dishing: Low pattern density regions polish slower while isolated wide copper lines suffer concave dishing: $h_{dish} \propto \left(\frac{W_{wire}}{W_{wire} + S}\right) \cdot P^{1.2} \cdot t_{overpolish}$. Inserting dummy fill maintains pattern density within a narrow $40\% - 60\%$ window across $20\,\mu\text{m} \times 20\,\mu\text{m}$ sliding windows.
Keepout Buffer Rules: Floating metal tiles must maintain a minimum keepout buffer ($S_{keepout} \ge 1.5 \cdot W_{fill}$) from active functional signal lines to eliminate parasitic capacitive coupling and cross-talk.

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