Silicon MEMS DRIE Bosch Etch Phototool & Vector Prepress CAM Guide

Comprehensive engineering reference for silicon Bosch etching, time-multiplexed SF6/C4F8 cycle optimization, ARDE compensation, and clean phototool DXF exports.

1. Deep Reactive Ion Etching (DRIE) Bosch Process Mechanics

The time-multiplexed Bosch process (also known as pulsed DRIE) achieves near-vertical sidewall profiles ($89.5^\circ - 90.5^\circ$) in bulk monocrystalline silicon by alternating sequentially between two distinct plasma chemical steps:

• Etch Step ($ ext{SF}_6$): High-density fluorine radicals spontaneously etch exposed silicon chemically, while energetic ion bombardment from the RF substrate bias accelerates bottom-trench vertical etching.
• Passivation Step ($ ext{C}_4 ext{F}_8$): A uniform fluorocarbon polymeric Teflon-like film ($( ext{CF}_2)_n$) is deposited conformally across all sidewalls and floor surfaces.

Subsequent directional ion bombardment easily sputters the thin polymer film from horizontal trench bottoms while leaving the vertical sidewalls protected from lateral chemical etching.

2. Aspect Ratio Dependent Etch Lag (ARDE) Formulations

As micro-trench aspect ratios ($AR = H/W$) exceed $10:1$, neutral radical conductance into deep trenches is severely throttled by Knudsen diffusion, producing Aspect Ratio Dependent Etching (ARDE):

R_eff = R_Si_open * (1 - K_lag * ln(H / W))
lambda_scallop = (R_Si / 60) * t_etch
T_PR_mask = (H_target / Selectivity_PR) * 1.20

Wide scribe lines etch significantly faster than sub-micron comb fingers. To prevent severe over-etching or punch-through, CAD mask designers must compensate aperture widths or add dummy load structures across the layout.

3. DRIE Process Parameter Optimization Matrix

4. Vector Phototool Prepress & CAD/CAM Mask Layout Rules

1. Corner Undercut Compensation: Add serif tabs ($+15\% - 25\%$ width) at external $90^\circ$ corners to counteract 2D plasma radical concentration.
2. ARDE Density Uniformity: Populate empty wafer areas with uniform dummy square tile vectors ($30\% - 50\%$ open area) to equalize global etching loads.
3. 1-Bit Binary Mask Export: Generate clean closed polygon DXF/GDSII layers with zero self-intersections or unclosed endpoints.