Micro-Electronics & Semiconductor Packaging

Semiconductor Stealth Dicing & Laser Scribing Street Calculator

Engineering calculator for semiconductor laser stealth dicing (SD) and multi-photon subterranean wafer separation. Computes internal focal depth ($z = n_r \cdot z_0$), subterranean modified layer count, pulse pitch, dicing street reduction, and gross die yield increases.

1. Input Parameters

Wafer Substrate Material

Wafer Thickness T (µm)

Die Size X (mm)

Die Size Y (mm)

Laser Scan Speed (mm/s)

Pulse Repetition Rate (kHz)

2. Calculation Results

Pulse Pitch (Spot Spacing)

-- µm

SD Modified Layers

-- Layers

Street Width Reduction

-- µm

Gross Die Gain (DPW)

+-- %

Bottom Focal Depth z

-- µm

Tape Expansion Strain

-- %

3. Geometric Visualizer

Tooling & Vector Prepress Engineering Notes

Subterranean Multi-Photon Stealth Dicing: Unlike mechanical diamond blade dicing that produces wide kerf loss ($60-100\,\mu\text{m}$), silicon chipping, and slurry contamination, Stealth Dicing (SD) utilizes a permeable infrared laser ($\lambda = 1064\text{ nm}$ or $1342\text{ nm}$) focused strictly inside the substrate interior. Non-linear multi-photon absorption creates localized micro-perforations (SD modified layers) with zero surface ablation.

Dicing Street Reduction & Silicon Yield: By shrinking the required scribe street from $80\,\mu\text{m}$ (blade) down to $<15\,\mu\text{m}$ (stealth dicing), semiconductor foundries achieve $+6\%$ to $+18\%$ higher gross die per wafer (DPW), generating millions in reclaimed silicon area for high-density ICs, LiDAR sensors, and power MOSFETs.

Tensile Tape Expansion Separation: Following multi-layer internal laser scanning, the dicing tape under the wafer is radially stretched in a mechanical tape expander (strain $\epsilon = 8\% - 12\%$, speed $5 - 20\text{ mm/s}$), propagating clean vertical cleavage fractures through the full wafer thickness with zero debris.